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The page table structure used by x CPUs when operating in long mode further extends the page table hierarchy to four levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space.

It also uses the topmost bit of the bit page table entry as a no-execute or “NX” bit , indicating that code cannot be executed from the associated page. The NX feature is also available in protected mode when these CPUs are running a bit operating system, provided that the operating system enables PAE.

PAE was first implemented in the Intel Pentium Pro in , [3] although the accompanying chipsets usually lacked support for the required extra address bits. When the x processor is initialized, the PAE feature is required to be enabled before the processor is switched from Legacy Mode to Long Mode.

With PAE, the page table entry of the x86 architecture is enlarged from 32 to 64 bits. This allows more room for the physical page address, or “page frame number” field, in the page table entry.

In the initial implementations of PAE the page frame number field was expanded from 20 to 24 bits. The size of the “byte offset” from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits i. In the first processors that supported PAE, support for larger physical addresses is evident in their package pinout, with address pin designations going up to A35 instead of stopping at A The bit size of the virtual address is not changed, so regular application software continues to use instructions with bit addresses and in a flat memory model is limited to 4 gigabytes of virtual address space.

Operating systems supporting this mode use page tables to map the regular 4 GB virtual address space into the physical memory, which, depending on the operating system and the rest of the hardware platform, may be as big as 64 GB.

The mapping is typically applied separately for each process , so that the additional RAM is useful even though no single process can access it all simultaneously.

Later work associated with AMD’s development of x architecture expanded the theoretical possible size of physical addresses to 52 bits. In protected mode with paging enabled bit 31, PG , of control register CR0 is set , but without PAE, x86 processors use a two-level page translation scheme.

Control register CR3 holds the page-aligned physical address of a single 4 KB long page directory. This is divided into four-byte page directory entries that in turn, if valid, hold the page-aligned physical addresses of page tables , each 4 KB in size.

These similarly consist of four-byte page table entries which, if valid, hold the page-aligned physical addresses of 4 KB long pages of physical memory RAM. By default, the size of each page remains as 4 KB. Each entry in the page table and page directory becomes 64 bits long 8 bytes , instead of 32 bits, to allow for additional address bits. However, the size of each table does not change, so both table and directory now have only entries.

Because this allows only one half of the entries of the original scheme, an extra level of hierarchy has been added, so CR3 now points physically to a Page Directory Pointer Table , a short table containing four pointers to page directories. The entries in the page directory have an additional flag in bit 7, named PS for page size.

If the system has set this bit to 1 , the page directory entry does not point to a page table but to a single, large 2 MB page Page Size Extension. In all page table formats supported by x86 and x , the 12 least significant bits of the page table entry are either interpreted by the memory management unit or are reserved for operating system use. In processors that implement the “no-execute” or “execution disable” feature, the most significant bit bit 63 is the NX bit. The next eleven most significant bits bits 52 through 62 are reserved for operating system use by both Intel and AMD’s architecture specifications.

Thus, from 64 bits in the page table entry, 12 low-order and 12 high-order bits have other uses, leaving 40 bits bits 12 though 51 for the physical page number. Combined with 12 bits of “offset within page” from the linear address, a maximum of 52 bits are available to address physical memory.

This allows a maximum RAM configuration of 2 52 bytes, or 4 petabytes about 4. On x processors in native long mode , the address translation scheme uses PAE but adds a fourth table, the entry page-map level 4 table, and extends the page directory pointer table to entries instead of the original 4 entries it has in protected mode.

Currently 48 bits of virtual page number are translated, giving a virtual address space of up to TB. A free-of-charge program for Microsoft Windows is available which will list many processor capabilities, including PAE support. To run the processor in PAE mode, operating system support is required.

According to Microsoft Technical Fellow Mark Russinovich , some drivers were found to be unstable when encountering physical addresses above 4GB.

However, it led to compatibility problems with 3rd party drivers which led Microsoft to remove this capability in Windows XP Service Pack 2. The Linux kernel includes full PAE-mode support starting with version 2. Linux distributions now commonly use a PAE-enabled kernel as the default, a trend that began in Support requires the kernel PAE configuration-option.

Not all drivers support more than 4 GB of physical memory; those drivers won’t work correctly on a system with PAE.

GeNUA mbH supported the initial implementation. Solaris supports PAE beginning with Solaris version 7. However, third-party drivers used with version 7 which do not specifically include PAE support may operate erratically or fail outright on a system with PAE.

From Wikipedia, the free encyclopedia. Memory management feature. This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. Intel Corporation. October February Retrieved Shanley Addison-Wesley Professional. ISBN Hardware Developers Center. Retrieved 20 April AMD Corporation.

Long-mode page translation requires the use of physical-address extensions PAE. PAE to 1. November Windows Sysinternals. October 8, December 5, Archived from the original on December 17, October 26, Knowledge Base.

Microsoft Docs. Retrieved 6 January April 26, Retrieved 24 October The non-PAE kernel will not be available in future Xubuntu releases. General Kernel Updates Retrieved 27 November To guarantee compatibility with non-PAE processors, the bit versions of Linux Mint Debian come with a kernel by default. Supported Hardware”. Categories : X86 architecture Virtual memory Memory management X86 memory management.

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